1. Field of the Invention
The present invention relates to a driver circuit for semiconductor switching device such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
2. Description of the Related Art
FIGS. 3A to 3C are circuit diagrams schematically showing the operation of conventional semiconductor switching devices. Switching devices Qa and Qb are connected in series between a power line (e.g., 300 V) of a power supply PS and a ground line (e.g., 0 V) in the totem pole configuration, where an output voltage Vout supplied to a load varies by alternately switching devices Qa and Qb. More specifically, when the source switching device Qa on the side of the power line turns on while the sink switching device Qb on the side of the ground line turns off, the output voltage Vout rises up to a voltage near the power-supply voltage of 300 V. On the other hand, when the switching device Qa turns off while the switching device Qb turns on, the output voltage Vout falls down to a voltage near the ground voltage of 0 V.
In case the switching devices Qa and Qb are configured of a voltage-driving type of semiconductor switching device such as IGBT and MOSFET, the capacitance C1 between the gate and the collector and the capacitance C2 between the gate and the emitter become relatively large. Such an influence must be reckoned with.
First, referring to FIG. 3A, when the gate voltage VGa of the switching device Qa is 0 V and the switching device Qa turns off while the gate voltage VGb of the switching device Qb is 15 V and the switching device Qb turns on, the capacitance C1 of the switching device Qa is charged at about 300 V voltages.
In FIG. 3B, when the gate voltage VGa is 315 V and the switching device Qa turns on while the gate voltage VGb is 0 V and the switching device Qb turns off, electric charge stored in the capacitance C1 of the switching device Qa passes through the switching device Qa, thereafter to be stored in the capacitance C1 of the switching device Qb. The charging current Ia is expressed by C1xc3x97(dv/dt), and the electric charge Q (=C1xc3x97V) is stored in the capacitance C1 of the switching device Qb.
In this case, since the parasitic resistance R exists in the gate of the switching device Qb, the gate voltage VGb rises up by the charging current Ia. The voltage rise-up xcex94VGb is expressed by the following equation:
Rxc3x97Ia=Rxc3x97C1xc3x97(dv/dt)
In FIG. 3C, when the gate voltage VGa is 300 V and the switching device Qa turns off while the gate voltage VGb is 15 V and the switching device Qb turns on, the electric charge stored in the capacitance C1 of the witching device Qb passes through the switching device Qb, thereafter to flow down to the ground line. On the other hand, the capacitance C1 of the switching device Qa is charged at about 300 V voltages. In this case, since the parasitic resistance R (i.e., interconnect parasitic resistance and on-resistance of MOSFET in a gate sink circuit) also exists in the gate of the switching device Qa, the gate voltage VGa rises up by the charging current flowing into the capacitance C1.
In general, the pre-stage of the switching devices Qa and Qb is provided with a gate driver circuit for driving each of their gates. When a sink transistor of the gate driver circuit comprises an emitter follower circuit (common collector), the gate voltage of the sink transistor rises up in accordance with the voltage rise-up xcex94VGb. In FIG. 3B, the gate voltage VGb of the switching device Qb does not fully fall down to 0 V and a so-called tail voltage is generated. A gate sink circuit is generally provided to prevent the above gate voltage rise-up.
FIG. 4A is a circuit diagram showing an example of a conventional gate sink circuit, and FIG. 4B is a timing diagram showing the operation thereof. A gate driver circuit B1 includes a source-side transistor Q1 such as a p-type MOSFET and a sink-side transistor Q2 such as an n-type MOSFET, which are complementarily connected in series to drive the gate of a switching device Q3. An inverter G1 inverts an input signal supplied to an input terminal Tin to supply the inverted signal to the gate driver circuit B1.
The operation of the gate driver circuit B1 will be described. When the input voltage vin is at high level, the transistor Q1 of the gate driver circuit B1 turns on while the transistor Q2 turns off, so that the gate voltage VG of the switching device Q3 becomes high level, as a result the switching device Q3 turns on.
Next, when the input voltage Vin becomes low level, the transistor Q1 turns off while the transistor Q2 turns on, so that the gate voltage VG also becomes low level, as a result the switching device Q3 turns off.
Thus the switching device Q3 can make conduction or cut off alternatively in response to the input signal level.
A gate sink circuit B2 includes a comparator CMP, a sink switching device Qs such as an n-type MOSFET and an inverter G2. The comparator CMP monitors the gate voltage VG of the switching device Q3 and compares the gate voltage with a predetermined threshold voltage Vth. The sink switching device Qs is connected between the gate of the switching device Q3 and the ground line. The inverter G2 inverts an output of the comparator CMP to drive the sink switching device Qs. The threshold voltage Vth for the comparator CMP is set by the expression, power supply voltage Vccxc3x97(division ratio of resistors R3 and R4).
The operation of the gate sink circuit B2 will be described below. Referring to FIG. 4B, when the input voltage Vin is at high level, the gate voltage VG is higher than the threshold voltage Vth of the comparator CMP. Thus, the output of the comparator CMP is high level while the output of the inverter G2 is low level, therefore the sink switching device Qs turns off.
When the input voltage Vin changes from high level to low level at the time t1, the switching device Q3 turns off, which corresponds to the transition state from FIG. 3A to FIG. 3B. Whereupon, the charging current flows to the capacitance between the gate and collector of the switching device Q3 and the tail voltage is generated in the gate voltage VG. The charging current decreases thereafter, when the gate voltage VG becomes lower than the threshold voltage Vth of the comparator CMP at the time t2, the output of the comparator CMP inverts into low level. As a result, the output of the inverter G2 becomes high level and the sink switching device Qs turns on. The gate of the switching device Q3 is conducted to the ground line, so that the gate voltage VG can be stabilized at the ground voltage.
Next, when the input voltage Vin changes from low level to high level at the time t5, the switching device Q3 turns on, which corresponds to the transition state from FIG. 3B to FIG. 3C. Whereupon, a discharge current flows from the capacitance between the gate and collector of the switching device Q3 and the gate voltage VG gradually rises up. When the discharge current decreases and the gate voltage VG becomes higher than the threshold voltage Vth of the comparator CMP at the time t6, the output of the comparator CMP inverts to high level. Thus, the output of the inverter G2 becomes low level and the sink switching device Qs turns off. The gate of the switching device Q3 is cut off from the ground line.
The following reference documents related to the prior art are given: Japanese Patent Unexamined Publication JPA-03-3415(1991), p.6 , FIG. 1; JPA-08-18423(1996), FIG. 1; JPA-09-298870(1997), FIG. 1; JPA-2000-197343(2000), FIG. 1.
In the case the on-resistance of the sink switching device Qs is relatively large, variations of the gate voltage VG can not be sufficiently suppressed when the charging current flowing into the capacitance between the gate and collector of the switching device Q3 becomes large at the time t2 in FIG. 4B.
In addition, at the time t3 to t4 in FIG. 4B, when the gate voltage of a source-side switching device coupled with the switching device Q3 rises up, which influences also the gate voltage VG to increase. If the gate voltage VG at that time exceeds the threshold voltage Vth of the comparator CMP, the sink switching device Qs turns off and the gate sink circuit B2 has no operation.
As described above, a switching device having a large capacity and small on-resistance is needed as the sink switching device Qs in order to securely bypass the current flowing into the gate of the switching device Q3 to the ground line.
Moreover, at the time t5 to t6 in FIG. 4B, the transistor Q1 in the gate driver circuit B1 tunes on and the sink switching device Qs also turns on. Therefore, large flow-through current passes through both the transistor Q1 and the sink switching device Qs, resulting in reduction of power efficiency.
Incidentally, the driver circuit for semiconductor switching devices described in related prior art (e.g., the above reference documents) has a different gate sink circuit in configuration.
An object of the present invention is to provide a driver circuit for semiconductor switching device, which can securely keep an off-state of a semiconductor switching device, and can greatly reduce flow-through current in turn-on.
According to one aspect of the present invention, there is provided a driver circuit for semiconductor switching device, comprising:
a gate driver circuit for driving the gate of a semiconductor switching device in response to an input signal;
a comparator circuit for comparing a gate voltage of the semiconductor switching device with a predetermined threshold value;
a memory circuit capable of being set in response to inversion of an output of the comparator circuit and reset in response to inversion of the input signal; and
a gate sink device for stabilizing the gate voltage of the semiconductor switching device when the memory circuit is set.
According to another aspect of the present invention, there is provided a driver circuit for semiconductor switching device, comprising:
a gate driver circuit for driving the gate of a semiconductor switching device in response to an input signal;
a filter circuit for delaying the input signal;
a comparator circuit for comparing an output of the filter circuit with a predetermined threshold value; and
a gate sink device for stabilizing the gate voltage of the semiconductor switching device in accordance with the output of the comparator circuit.
According to the present invention, the off-state of the semiconductor switching device can be securely kept and flow-through current in turn-on can be greatly reduced, thereby improving power efficiency.